1. Field of Invention
This invention relates to methods of attaching semiconductor light emitting devices to other structures.
2. Description of Related Art
Semiconductor light-emitting devices including light emitting diodes (LEDs), resonant cavity light emitting diodes (RCLEDs), vertical cavity laser diodes (VCSELs), and edge emitting lasers are among the most efficient light sources currently available. Materials systems currently of interest in the manufacture of high-brightness light emitting devices capable of operation across the visible spectrum include Group III-V semiconductors; for example, binary, ternary, and quaternary alloys of gallium, aluminum, indium, nitrogen, phosphorus, and arsenic. III-V devices emit light across the visible spectrum. GaAs- and GaP-based devices are often used to emit light at longer wavelengths such as yellow through red while III-nitrite devices are often used to emit light at shorter wavelengths such as near-UV through green.
FIG. 1 illustrates a prior art package for a GaAs- or GaP-based device, described in more detail in U.S. Pat. No. 5,777,433. LED 10 includes a semiconductor LED chip 12 encapsulated by a package 11, typically a thermoset material such as epoxy or thermo-plastic material. A p-n junction 13 within LED chip 12 generates light. A pair of electrical contacts 15 and 16 connect to the LED chip 12, contact 16 by a wire bond 14, and contact 15 by, for example, epoxy. The epoxy connecting LED chip 12 to contact 15 makes device 10 suitable for only low temperature applications, since epoxy typically cannot tolerate high temperatures without degrading. In addition, epoxy has very high thermal resistance, thus the design of FIG. 1 provides only high resistance pathways for heat to escape LED chip 12, limiting device 10 to low power applications.
As semiconductor light emitting devices capable of operating at high power were developed, new packages which could tolerate higher heat and which could more efficiently remove heat from the semiconductor device are required. FIGS. 2 and 3 illustrate a cross sectional view and a plan view of a flip chip III-nitrite device, described in more detail in U.S. Pat. No. 6,486,499, which is incorporated herein by reference. The device of FIGS. 2 and 3 is a large-area, e.g.>400×400 μm2 LED with reduced thermal resistance from the p-n junction to the lamp package. The device of FIGS. 2 and 3 uses an inverted structure employing a low resistivity, opaque, highly reflective p-electrode.
In the cross-sectional view shown in FIG. 2, the device includes a III-nitrite epitaxial heterostructure of n-type and undoped layers 111 and p-type layers 12, each in contact with an active region 13. The III-nitrite layers 11 are optionally attached to a transparent substrate 10. The substrate 10 can be the growth substrate for deposition of the III-nitrite layers. In the plan view of the bottom of the LED die shown in FIG. 3, n-electrode 22 includes “fingers” interposing the p-electrode metallization 20 to spread current throughout the device. Light may be taken out of the device through the transparent substrate 10 due to a highly reflective, thick p-electrode metallization 20. The electrode metallizations connect to submount electrodes 52 on a submount substrate 50 via interconnects 60. The interconnects make electrical connection between the LED and the submount while providing a thermal path for heat removal from the LED during operation. The interconnects may be made of elemental metals, metal alloys, semiconductor-metal alloys, solders, thermally and electrically conductive pastes or compounds (e.g., epoxies), eutectic joints (e.g., Pd—In—Pd) between dissimilar metals between the LED die and submount, Au stud-bumps, or solder bumps.
The interconnects are attached to the LED and submount via conductive interfaces 41, 54. When solder is used as the interconnect, the conductive interfaces are wettable metals. An application process initially determines the interconnect thickness and area. One applicable technique is a screen-printing process where paste is applied to selected areas on the submount wafer or LED. Other techniques include electroplating, lift-off, and reflow. For an embodiment using solder as the interconnect, the final interconnect thickness and area are determined by the solder volume as well as the wettable metals 41 on the LED die and 54 on the submount. The solderable areas on the LED are defined through patterning of the wetting metals, or through vias in a patterned dielectric passivation layer 42 provided on the LED die. The dielectric passivation layer 42 acts as an electrical isolation layer between the p and n electrodes and is required since the solder layers 60 extend across both p and n electrodes. The solderable areas on the submount are similarly defined by patterning the solderable metals 54 or by providing a dielectric layer 51. A second set of solderable metal layers 55 may be deposited on the back of the submount for attachment to the remaining part of the package. Optionally, a suitable solder can be deposited directly on the back of the submount. The junction-to-package thermal resistance is largely governed by the die/submount solder joint and the submount material and geometry. Hence, it is desirable to cover the entire surface of the LED die with the solder. This is not possible as electrical isolation is required between the p and n electrode regions of the LED. Also, the width of this gap between the n and p solderable metals must account for tolerances in die attaching to the submount. Even so, the device of FIG. 3 provides about 85% solder coverage (defined as the ratio of solderable metal area 41 relative to the p electrode area 20).
Like the device illustrated in FIG. 1, the device illustrated in FIGS. 2 and 3 also has limited temperature operation, as it is limited to operating conditions below the melting point of solder layers 60. For example, typical solders such as eutectic SnPb and eutectic AuSn are limited to operating temperatures of 183° C. and 280° C., respectively. Also, attaching the semiconductor device to the submount as illustrated in FIG. 2 generally involves reflowing solder layers 60, typically by rapidly heating the semiconductor device and the submount to a temperature above the melting point of the solder. This process may damage the semiconductor device by introducing thermal stress. Further, solders are often alloys and often include Sn. Alloys typically have worse thermal conductivity than pure metals, and at elevated temperatures, Sn can damage the metal electrodes attached to the semiconductor layers.
Needed in the art are package connection designs and attach techniques which provide low thermal resistance, facilitate high temperature operation, do not require stressful processing conditions such as high process temperatures, and are inexpensive and easy to manufacture.